Manufacturing of integrated circuits depends intimately on the ability to test a manufactured circuit to determine if it is fully functional. These tests determine if a circuit is suffering from a variety of faults, including stuck-at faults and transition delay faults. Stuck-at faults are manufacturing flaws that force a circuit node to have a constant value contrary to the designer's intent. Transition delay faults are manufacturing flaws that result in a circuit node that is slower than designed to respond to stimulus resulting in improper circuit operation at the designed operating speed. Determining if a circuit has either or both types of flaws is a critical part of modern integrated circuit design. Design for Test (DFT) is a methodology that describes inserting test fixtures into a design as part of the original specification. Automatic Test Pattern Generation (ATPG) combined with scan-chain insertion is a well-understood DFT method for creating patterns that when applied to a circuit are able to detect stuck-at faults. A variety of ad-hoc transition fault detection methods that leverage existing DFT structures are used in the industry.
In integrated circuit delay and stuck-at fault testing RAMs present a particular challenge since they are not easily loaded and unloaded. That is, RAMs do not have a simple load mechanism such as scan enable and scan in, nor a simple unload method such as scan enable and scan out. Rather, RAMs must be loaded with data via control, address and data inputs and the outputs driven by known data via a similar mechanism. In classic stuck-at or delay fault testing this provides a challenge because ensuring that the correct control signals are on the RAM input and output pins is difficult.
Delay fault test time is often dominated by scan-chain load sequences where the scan data is read from the tester into the device, particularly when the test vectors are targeting specific faults later in the test sequence. A means to reduce or minimize the number of load cycles will generally save tester time and cost.
Delay fault coverage is also affected by the operating conditions of the integrated circuit including phenomena such as temperature and power mesh response. As such the initialization vector (IV)-transition vector (TV) vector sequence many not accurately reflect the normal operating conditions of an integrated circuit resulting in overly pessimistic or optimistic fault coverage depending on the circuits response when exposed to the new operating conditions.
DFT strategies often have area and wiring overhead as a result of logical functionality to perform the strategy as well as the wiring required to connect the DFT structures. Minimizing the area and wiring overhead associated with DFT strategies is a concern.